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The primary and secondary serial communications ports are accessible through the QScreen's 10 pin, dual row Serial Header (H5) which is typically not installed, the 24 pin, dual row Field Header (H3), and through the individual DB-9 Serial 1 and Serial 2 connectors. Configured as a master device, the 68HC11 transmits bytes via the "master out/slave in" pin, MOSI. Regardless of the network, however, there are only four signals used: SCK provides a synchronized clock, MOSI and MISO signals are used for data transmission and reception, and /SS configures the 68HC11 as a master or slave device. Regardless of the network, however, there are only four signals used: SCK provides a synchronized clock, MOSI and MISO signals are used for data transmission and reception, and /SS configures the QScreen as a master or slave device. If the /SS pin of the master is an output, it can be controlled independently of the SPI system. If bit 5 of DDRD is 1, then /SS is a general purpose output that operates independently of the SPI. If the CPHA bit is 1, the /SS line may be tied low between successive transfers. It is a half duplex protocol, meaning that only one party at a time may transmit data.

Multiple receivers may be connected to such a network in a linear, multidrop bus. What made it such an advancement over RS232 was the fact that it could transmit not only a single device to device transmission, but also a communications bus to connect multiple devices at once. This allows RS-485 to implement linear bus topologies using only two wires. Serial 2 is implemented by a software UART in the controller’s QED-Forth Kernel that uses two of the processor’s PortA I/O pins to generate a serial communications channel. There are surface mount resistor pads on the QScreen that will allow you to bring out the secondary serial port to the Field Header on pins 5-6 or 7-8 as shown with the parentheses in Table 11-3. Pads are also available to bring out the RS485 signals to the DB9 Serial 1 Connector. To provide a convenient means of attaching two grounds to the serial cable, there are several pins (labeled GND) on the communications connector that are connected to the controller’s ground plane. Many times the old DB-9 connector is used. The /SS input in turn determines whether the slave responds to the SCK input, as described in a previous section.

If you've already downloaded and installed the Software, go to the section called "Upgrading the Modules". The next section describes the registers that configure and control the QVGA Controller’s SPI. The QScreen Controller combines an embedded computer based on the 68HC11 microcontroller with a touch panel and LCD (liquid crystal display) graphic user interface (GUI) that is ideal for instrument control and automation. We have built sophisticated instruments using the QScreen Controller that operate very reliably using multiple interrupts in addition to the software UART. The WattNode® BACnet and Modbus® meters communicate using RS-485 (TIA/EIA-485-A) half-duplex, differential signaling at 9600, 19200, 38400, and 76,800 baud. Use Laurel’s 6-wire data cables CBL03-1 (1 ft) and CBL03-7 (7 ft) to interconnect meters if these lengths fit your application. RS232’s greatest benefit is its universality; practically all personal computers can use this protocol to send and receive serial data. It is supported by virtually all personal computers, and is the default protocol for both of the QScreen Controller’s serial ports.

The QScreen Controller does not differentiate between these. RS485 is another protocol supported by the primary serial port on the QScreen Controller. In this example, the QVGA Controller selects the serial A/D by outputting a LOW signal on /SS. If the /SS input to a slave is active (low), the slave transfers data in response to the SCK clock input that is initiated by the master. Thus, the master 68HC11 has only one input, MISO, which is the slave QVGA Controller’s only output. Any required SPI output signals must be configured as outputs by setting the appropriate bits in the Port D data direction register which is named PORTD.DIRECTION in the QED-Forth kernel. If the 68HC11 is initialized as a master (by setting the MSTR bit in the SPCR control register as explained below) then bit 5 of the Port D data direction register (DDRD) determines whether /SS is an input or an output.

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